Digital circuits are typically interfaced with an asynchronous input signal by a synchronizer circuit to synchronize the input signal with a system clock or derivative thereof. A common problem with synchronizer circuits involves the reliable reading of asynchronous data which is transitioning during the change of the system clock. Such circuits often either incorrectly interpret the logic state of the input data or read the data as an indeterminate state. Previous synchronizer circuits have used a plurality of stages to obtain enough voltage gain to make a logic level determination. However, the plurality of stages generally requires a large amount of circuitry and is typically slow in providing a synchronized data signal because of clock delays. Other synchronizer circuits which are fast such as the synchronizer taught by Shaw et al. in U.S. Pat. No. 4,317,053 and assigned to the assignee hereof may be improved by using less circuitry.